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1e0e96f9a0
litex
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litex
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Florent Kermarrec
1e0e96f9a0
interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods.
2020-02-28 16:25:09 +01:00
..
boards
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:48:48 +01:00
build
lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends.
2020-02-28 08:32:29 +01:00
gen
gen/fhdl/verilog: fix signed init values
2020-01-12 22:06:35 +01:00
soc
interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods.
2020-02-28 16:25:09 +01:00
tools
tools: litex_gen: fix missing UART pins
2020-02-25 14:24:29 +01:00
__init__.py
soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)
2019-09-30 23:41:07 +02:00