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1e6d1deae8
litex
/
misoclib
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com
/
uart
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test
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Florent Kermarrec
bd4d3cd73b
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
2015-03-01 12:14:34 +01:00
..
test_serial_phy.py
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
2015-03-01 12:14:34 +01:00