Sebastien Bourdeauducq 1eb348c573 fhdl: do not attempt slicing non-array signals to keep Verilog happy		2012-02-06 18:07:02 +01:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
autofragment.py	Pay a bit more attention to PEP8	2011-12-16 16:02:55 +01:00
namer.py	fhdl/namer: Add support for STORE_DEREF opcode	2012-02-02 21:15:10 +01:00
structure.py	fhdl/structure: binary constant builder	2012-02-05 19:32:11 +01:00
tools.py	fhdl/verilog: clean up signal classification and support memory descriptions	2012-01-27 16:54:48 +01:00
verilog.py	fhdl: do not attempt slicing non-array signals to keep Verilog happy	2012-02-06 18:07:02 +01:00
verilog_mem_behavioral.py	fhdl: support memory read enable	2012-01-27 21:39:23 +01:00