litex/misoclib/mem/sdram
Florent Kermarrec ff11cb97a9 sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True 2015-03-25 17:22:26 +01:00
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core sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True 2015-03-25 17:22:26 +01:00
frontend sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest) 2015-03-02 10:59:43 +01:00
phy sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy 2015-03-25 16:57:38 +01:00
test sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings. 2015-03-25 16:56:29 +01:00
__init__.py sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings. 2015-03-25 16:56:29 +01:00
module.py sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy 2015-03-25 16:57:38 +01:00