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Build your hardware, easily!
48 Commits 40 Branches 14 Tags 51 MiB
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Python 43.5%
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Sebastien Bourdeauducq 22d03b4943 timeline: only trigger in rest state 2011-12-13 15:25:46 +01:00
examples examples: Wishbone interconnect test bench 2011-12-13 14:10:56 +01:00
migen timeline: only trigger in rest state 2011-12-13 15:25:46 +01:00
.gitignore Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00