Florent Kermarrec eb9f54b2bc test: add initial (minimal) test for clock abstraction modules. ... Also fix divclk_divide_range on S6DCM.		2020-03-13 12:38:23 +01:00
..
__init__.py	…
test_axi.py	soc/interconnect/axi: add Wishbone2AXILite	2019-11-20 12:32:22 +01:00
test_bitbang.py	…
test_clock.py	test: add initial (minimal) test for clock abstraction modules.	2020-03-13 12:38:23 +01:00
test_code_8b10b.py	…
test_csr.py	soc/interconnect/csr: add initial field support	2019-09-13 20:01:31 +02:00
test_ecc.py	…
test_gearbox.py	…
test_hyperbus.py	soc/core: simplify/cleanup HyperRAM core	2019-08-16 14:04:58 +02:00
test_i2s.py	soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores.	2020-02-06 17:00:04 +01:00
test_icap.py	soc/cores/icap: simplify ICAPBitstream (untested)	2019-10-01 21:30:14 +02:00
test_packet.py	test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer	2019-11-16 14:39:18 +01:00
test_prbs.py	…
test_spi.py	core/spi: add minimal SPISlave	2019-08-29 09:46:20 +02:00
test_spi_opi.py	soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now)	2020-02-06 17:58:01 +01:00
test_stream.py	interconnect/stream: add PipeValid and PipeWait to cut timing paths.	2020-01-29 18:27:29 +01:00
test_targets.py	test/test_targets: use uart-name=stub.	2020-02-29 11:07:10 +01:00