Florent Kermarrec 27c55999c6 gen/common/colorer: Add enable parameter to allow enabling/disabling coloring.		2023-11-03 11:05:09 +01:00
..
fhdl	gen/fhdl/verilog: Rename _print_xy to _generate_xy and cleanup imports.	2023-11-03 10:14:38 +01:00
genlib	gen/genlib/misc/WaitTimer: Cast t to int and minor cosmetic cleanup.	2023-07-31 11:27:47 +02:00
sim	gen/fhdl: Integrate namer from Migen to give us more flexibility on generated verilog names.	2022-05-06 16:04:24 +02:00
__init__.py	litex/gen: Split common in common/context/reduce/signal.	2023-07-27 15:02:37 +02:00
common.py	gen/common/colorer: Add enable parameter to allow enabling/disabling coloring.	2023-11-03 11:05:09 +01:00
context.py	litex/gen: Add some comments.	2023-07-27 16:18:30 +02:00
reduce.py	litex/gen: Split common in common/context/reduce/signal.	2023-07-27 15:02:37 +02:00
signal.py	litex/gen: Add some comments.	2023-07-27 16:18:30 +02:00