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28b0c340af
litex
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migen
History
Sebastien Bourdeauducq
28b0c340af
corelogic/record: add to_signal convenience function
2012-02-11 20:55:23 +01:00
..
actorlib
Use enumerate(x) instead of zip(range(x), x)
2012-02-02 21:28:00 +01:00
bank
bank: event manager
2012-02-06 17:39:32 +01:00
bus
bus/asmibus: add get_slots, fix get_fragment
2012-02-10 17:49:06 +01:00
corelogic
corelogic/record: add to_signal convenience function
2012-02-11 20:55:23 +01:00
fhdl
fhdl: do not attempt slicing non-array signals to keep Verilog happy
2012-02-06 18:07:02 +01:00
flow
Use enumerate(x) instead of zip(range(x), x)
2012-02-02 21:28:00 +01:00
__init__.py
Initial import, FHDL basic structure, divider example
2011-12-04 16:44:38 +01:00