Sebastien Bourdeauducq 280a87ea69 elsewhere: do not create interface in default param		2012-12-06 17:34:48 +01:00
..
__init__.py	…
asmibus.py	Replace Signal(bits_for(... with Signal(max=...	2012-11-29 21:53:36 +01:00
csr.py	elsewhere: do not create interface in default param	2012-12-06 17:34:48 +01:00
dfi.py	Remove Constant	2012-11-28 23:18:43 +01:00
memory.py	bus: memory initiator	2012-11-23 16:22:50 +01:00
simple.py	New specification for width and signedness	2012-11-29 21:22:38 +01:00
transactions.py	bus/transactions: add busname parameter	2012-11-17 19:36:08 +01:00
wishbone.py	elsewhere: do not create interface in default param	2012-12-06 17:34:48 +01:00
wishbone2asmi.py	New specification for width and signedness	2012-11-29 21:22:38 +01:00
wishbone2csr.py	bus/csr: configurable data width	2012-08-26 21:19:34 +02:00