litex/migen
Sebastien Bourdeauducq 28b4d99d31 replace some forgotten is_abstract() 2012-12-12 22:36:45 +01:00
..
actorlib actorlib/sim: drive busy high until generator is finished 2012-12-05 16:40:12 +01:00
bank migen/bank: do not create interface in default param 2012-12-06 17:28:28 +01:00
bus elsewhere: do not create interface in default param 2012-12-06 17:34:48 +01:00
corelogic corelogic/roundrobin: fix request width (again) 2012-11-29 23:47:51 +01:00
fhdl fhdl/structure: do not create Signal in Instance when parameter is int 2012-12-06 20:56:46 +01:00
flow replace some forgotten is_abstract() 2012-12-12 22:36:45 +01:00
pytholite pytholite: fix bit width of selection signal 2012-11-30 17:07:32 +01:00
sim New specification for width and signedness 2012-11-29 21:22:38 +01:00
uio pytholite/io: support memory 2012-11-23 20:36:09 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00