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Sebastien Bourdeauducq 28f00c3a9a Add on-chip SRAM 2012-01-27 22:09:03 +01:00
build Initial import 2011-12-13 17:33:12 +01:00
milkymist Add on-chip SRAM 2012-01-27 22:09:03 +01:00
tb/norflash Convert -> convert 2012-01-05 19:27:45 +01:00
verilog uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
.gitignore Initial import 2011-12-13 17:33:12 +01:00
build.py Convert -> convert 2012-01-05 19:27:45 +01:00
constraints.py Multiply system clock 2011-12-17 15:00:18 +01:00
top.py Add on-chip SRAM 2012-01-27 22:09:03 +01:00