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litex
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https://github.com/enjoy-digital/litex.git
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Build your hardware, easily!
fpga
hardware
system-on-chip
16
Commits
42
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14
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30
MiB
C
52.7%
Python
43.6%
Assembly
1.4%
SystemVerilog
1.3%
Makefile
0.3%
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28f00c3a9a
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Sebastien Bourdeauducq
28f00c3a9a
Add on-chip SRAM
2012-01-27 22:09:03 +01:00
build
Initial import
2011-12-13 17:33:12 +01:00
milkymist
Add on-chip SRAM
2012-01-27 22:09:03 +01:00
tb
/norflash
Convert -> convert
2012-01-05 19:27:45 +01:00
verilog
uart: new design using FHDL and bank (TX only, incomplete)
2011-12-18 00:29:37 +01:00
.gitignore
Initial import
2011-12-13 17:33:12 +01:00
build.py
Convert -> convert
2012-01-05 19:27:45 +01:00
constraints.py
Multiply system clock
2011-12-17 15:00:18 +01:00
top.py
Add on-chip SRAM
2012-01-27 22:09:03 +01:00