Sebastien Bourdeauducq 4164fb4ac9 bus/csr: configurable data width		2012-08-26 21:19:34 +02:00
..
__init__.py
asmibus.py	bus/asmibus: fix per-port tag generation	2012-07-12 19:37:50 +02:00
csr.py	bus/csr: configurable data width	2012-08-26 21:19:34 +02:00
dfi.py
simple.py
transactions.py
wishbone.py	x.bv.width -> len(x)	2012-07-13 18:32:54 +02:00
wishbone2asmi.py
wishbone2csr.py	bus/csr: configurable data width	2012-08-26 21:19:34 +02:00