Sebastien Bourdeauducq 2e14569b5c fhdl/verilog: sort clock domains by name		2012-09-11 10:00:03 +02:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
autofragment.py	Pay a bit more attention to PEP8	2011-12-16 16:02:55 +01:00
namer.py	fhdl/namer: better handling of indices	2012-09-09 19:33:55 +02:00
structure.py	fhdl: list signals in execution order	2012-09-11 09:59:37 +02:00
tools.py	fhdl: list signals in execution order	2012-09-11 09:59:37 +02:00
tracer.py	fhdl/namer: better handling of indices	2012-09-09 19:33:55 +02:00
verilog.py	fhdl/verilog: sort clock domains by name	2012-09-11 10:00:03 +02:00
verilog_mem_behavioral.py	Multi-clock design support + new instance API	2012-09-10 23:45:02 +02:00