145 lines
3.8 KiB
Python
145 lines
3.8 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.roundrobin import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import optree
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from migen.genlib.fifo import SyncFIFO
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from misoclib.lasmicon.multiplexer import *
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class _AddressSlicer:
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def __init__(self, col_a, address_align):
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self.col_a = col_a
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self.address_align = address_align
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def row(self, address):
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split = self.col_a - self.address_align
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if isinstance(address, int):
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return address >> split
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else:
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return address[split:]
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def col(self, address):
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split = self.col_a - self.address_align
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if isinstance(address, int):
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return (address & (2**split - 1)) << self.address_align
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else:
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return Cat(Replicate(0, self.address_align), address[:split])
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class BankMachine(Module):
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def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
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self.refresh_req = Signal()
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self.refresh_gnt = Signal()
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self.cmd = CommandRequestRW(geom_settings.mux_a, geom_settings.bank_a)
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###
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# Request FIFO
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self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], timing_settings.req_queue_size)
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self.comb += [
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self.req_fifo.din.we.eq(req.we),
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self.req_fifo.din.adr.eq(req.adr),
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self.req_fifo.we.eq(req.stb),
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req.req_ack.eq(self.req_fifo.writable),
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self.req_fifo.re.eq(req.dat_ack),
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req.lock.eq(self.req_fifo.readable)
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]
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reqf = self.req_fifo.dout
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slicer = _AddressSlicer(geom_settings.col_a, address_align)
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# Row tracking
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has_openrow = Signal()
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openrow = Signal(geom_settings.row_a)
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hit = Signal()
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self.comb += hit.eq(openrow == slicer.row(reqf.adr))
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track_open = Signal()
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track_close = Signal()
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self.sync += [
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If(track_open,
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has_openrow.eq(1),
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openrow.eq(slicer.row(reqf.adr))
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),
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If(track_close,
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has_openrow.eq(0)
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)
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]
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# Address generation
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s_row_adr = Signal()
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self.comb += [
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self.cmd.ba.eq(bankn),
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If(s_row_adr,
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self.cmd.a.eq(slicer.row(reqf.adr))
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).Else(
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self.cmd.a.eq(slicer.col(reqf.adr))
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)
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]
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# Respect write-to-precharge specification
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precharge_ok = Signal()
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t_unsafe_precharge = 2 + timing_settings.tWR - 1
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unsafe_precharge_count = Signal(max=t_unsafe_precharge+1)
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self.comb += precharge_ok.eq(unsafe_precharge_count == 0)
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self.sync += [
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If(self.cmd.stb & self.cmd.ack & self.cmd.is_write,
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unsafe_precharge_count.eq(t_unsafe_precharge)
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).Elif(~precharge_ok,
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unsafe_precharge_count.eq(unsafe_precharge_count-1)
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)
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]
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# Control and command generation FSM
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fsm = FSM()
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self.submodules += fsm
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fsm.act("REGULAR",
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If(self.refresh_req,
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NextState("REFRESH")
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).Elif(self.req_fifo.readable,
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If(has_openrow,
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If(hit,
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# NB: write-to-read specification is enforced by multiplexer
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self.cmd.stb.eq(1),
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req.dat_ack.eq(self.cmd.ack),
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self.cmd.is_read.eq(~reqf.we),
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self.cmd.is_write.eq(reqf.we),
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self.cmd.cas_n.eq(0),
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self.cmd.we_n.eq(~reqf.we)
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).Else(
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NextState("PRECHARGE")
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)
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).Else(
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NextState("ACTIVATE")
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)
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)
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)
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fsm.act("PRECHARGE",
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# Notes:
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# 1. we are presenting the column address, A10 is always low
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# 2. since we always go to the ACTIVATE state, we do not need
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# to assert track_close.
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If(precharge_ok,
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self.cmd.stb.eq(1),
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If(self.cmd.ack, NextState("TRP")),
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self.cmd.ras_n.eq(0),
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self.cmd.we_n.eq(0),
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self.cmd.is_cmd.eq(1)
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)
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)
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fsm.act("ACTIVATE",
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s_row_adr.eq(1),
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track_open.eq(1),
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self.cmd.stb.eq(1),
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self.cmd.is_cmd.eq(1),
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If(self.cmd.ack, NextState("TRCD")),
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self.cmd.ras_n.eq(0)
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)
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fsm.act("REFRESH",
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self.refresh_gnt.eq(precharge_ok),
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track_close.eq(1),
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self.cmd.is_cmd.eq(1),
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If(~self.refresh_req, NextState("REGULAR"))
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)
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fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1)
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fsm.delayed_enter("TRCD", "REGULAR", timing_settings.tRCD-1)
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