litex/misoclib/mem/litesata/example_designs
Sebastien Bourdeauducq ff29c86fe1 litesata/kc705: use FMC pin names 2015-03-03 01:02:50 +00:00
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platforms litesata/kc705: use FMC pin names 2015-03-03 01:02:50 +00:00
targets liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
test liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
make.py litesata: create example design derived from SoC 2015-03-01 11:33:38 +01:00