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2f7206b386
litex
/
misoclib
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mem
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sdram
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bus
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Florent Kermarrec
6b24562eea
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
2015-03-02 10:59:43 +01:00
..
dfi.py
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
lasmibus.py
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
2015-03-02 10:59:43 +01:00