litex/migen/bus
Sebastien Bourdeauducq 246b860a85 csr: new data width API 2013-07-28 16:33:36 +02:00
..
__init__.py CSR bus definitions 2011-12-05 00:16:44 +01:00
csr.py csr: new data width API 2013-07-28 16:33:36 +02:00
dfi.py dfi: split phase description 2013-07-10 19:56:47 +02:00
lasmibus.py lasmibus: fix master locking 2013-07-15 21:45:07 +02:00
memory.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
transactions.py New migen.fhdl.std to simplify imports + len->flen 2013-05-22 17:11:09 +02:00
wishbone.py bus/wishbone: configurable data width 2013-07-27 22:25:07 +02:00
wishbone2csr.py csr: new data width API 2013-07-28 16:33:36 +02:00
wishbone2lasmi.py FSM: new API 2013-06-25 22:17:39 +02:00