Florent Kermarrec 309eda4246 litex_term: keep and reduce inter-frame delay to 1e-5. ... Removing it completely would require revisiting the gateware/firmware code of the UART. Since this is use for test purpose only and already allow > 600KB/s upload speed, keeping it is acceptable.		2020-06-23 17:20:12 +02:00
..
boards	platforms/genesys2: use openocd_genesys2.cfg.	2020-06-23 11:58:36 +02:00
build	build/sim/core/modules: fix compilation warnings	2020-06-16 01:06:11 +02:00
gen	gen/fhdl/verilog: explicitly define input/output/inout wires.	2020-05-05 16:58:33 +02:00
soc	soc/cores/uart/FT245: only use Asynchronous FIFO (Synchronous FIFO requires a software configuration).	2020-06-23 16:53:17 +02:00
tools	litex_term: keep and reduce inter-frame delay to 1e-5.	2020-06-23 17:20:12 +02:00
__init__.py	litex/__init__.py: remove retro-compat > 6 months old.	2020-04-30 21:31:58 +02:00