This website requires JavaScript.
Explore
Help
Sign In
Hardware
/
litex
mirror of
https://github.com/enjoy-digital/litex.git
Watch
1
Star
0
Fork
You've already forked litex
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
30f1e77c18
litex
/
migen
History
Sebastien Bourdeauducq
30f1e77c18
corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time
2012-07-13 20:21:04 +02:00
..
actorlib
actorlib/dma_asmi: out-of-order reader and class factory
2012-07-12 18:34:13 +02:00
bank
Use super() instead of calling parent constructors directly
2012-06-08 18:06:12 +02:00
bus
x.bv.width -> len(x)
2012-07-13 18:32:54 +02:00
corelogic
corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time
2012-07-13 20:21:04 +02:00
fhdl
x.bv.width -> len(x)
2012-07-13 18:32:54 +02:00
flow
flow/perftools: refactor to use hooks
2012-07-06 23:36:23 +02:00
sim
x.bv.width -> len(x)
2012-07-13 18:32:54 +02:00
__init__.py
Initial import, FHDL basic structure, divider example
2011-12-04 16:44:38 +01:00