Sean Cross 32d5a751db soc_core: uart: add a reset line to the UART ... Enable resetting the UART by adding a ResetInserter to the UART. The UART must be reset when resetting the softcore. Signed-off-by: Sean Cross <sean@xobs.io>		2018-07-05 17:25:29 +08:00
..
cores	soc: vexriscv: add cpu debug support	2018-07-05 17:25:28 +08:00
integration	soc_core: uart: add a reset line to the UART	2018-07-05 17:25:29 +08:00
interconnect	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
software	bios/sdram: also check for last read of scan to choose optimal window	2018-07-02 14:12:27 +02:00
tools	litex_term: cleanup getkey and revert default settings on KeyboardInterrupt	2018-05-24 08:10:05 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
MISOC_LICENSE	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00