Florent Kermarrec 34b45e3618 gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework)		2016-02-11 22:54:26 +01:00
..
boards	boards/targets: change mode (add +x)	2016-01-01 18:37:20 +01:00
build	gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework)	2016-02-11 22:54:26 +01:00
gen	gen/build: use verilog 2001-style synthesis attributes for vivado (will need rework)	2016-02-11 22:54:26 +01:00
soc	soc/interconnect/stream: fix merge issue (missing params connect)	2016-02-01 00:08:27 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00