litex/litex
2020-12-10 14:34:00 +01:00
..
boards symbiflow: remove workarounds for symbiflow 2020-11-23 10:33:11 +01:00
build don't add pins without pad location in constraints file 2020-12-02 13:24:15 +01:00
gen gen/fhdl/verilog: improve clock domain error reporting. 2020-11-10 13:27:29 +01:00
soc integration/soc/add_uart: pass fifo_depth to UARTCrossover. 2020-12-10 14:33:29 +01:00
tools tools/litex_term/crossover: use burst to speed up reads. 2020-12-10 14:34:00 +01:00
__init__.py revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp). 2020-11-05 19:55:18 +01:00