_____       _            ____  _     _ _       _ 
            |   __|___  |_|___ _ _   |    \|_|___|_| |_ ___| |
            |   __|   | | | . | | |  |  |  | | . | |  _| .'| |
            |_____|_|_|_| |___|_  |  |____/|_|_  |_|_| |__,|_|
                      |___|   |___|          |___|
 
       Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
 
                                 Miscope
--------------------------------------------------------------------------------

[> Miscope
------------

Miscope is a small logic analyzer to embed in an FPGA.

While free vendor toolchains are generally used by beginners or for prototyping 
(situations where having a logic analyser in the design is generally helpful) 
free toolchains are always provided without the proprietary logic analyzer 
solution... :(

Based on Migen, Miscope aims to provide a free, portable and flexible 
alternative to vendor's solutions!

[> Specification:

Miscope provides Migen cores to embed in the design and Python drivers to control
the logic analyzer from the Host. Miscope automatically interconnects all cores 
to a CSR bus. When using Python on the Host, no needs to worry aboutcores register
mapping, importing miscope project gives you direct access to all the cores!

Miscope produces .vcd output files to be analyzed in your favorite waveform viewer.

Since Miscope also provides an Uart2Csr bridge, you only need 2 external Rx/Tx pins
to be ready to debug!

You should use the current Migen fork:
(http://github.com/Florent-Kermarrec/migen)

[> Status:
Miio & Mila working on board with standard term.
RLE working on board.
RangeDetector and EdgeDector terms not tested.

[> Examples:
test_Miio : Led & Switch Test controlled by Python Host.
test_Miia : Logic Analyzer controlled by Python Host.

[> Contact
E-mail: florent@enjoy-digital.fr