154 lines
3.6 KiB
Python
154 lines
3.6 KiB
Python
from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.fhdl.specials import Memory
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank.description import *
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class Term(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.sink = Sink([("d", width)])
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self.source = Source([("hit", 1)])
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self.busy = Signal()
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self._r_trig = CSRStorage(width)
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self._r_mask = CSRStorage(width)
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###
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trig = self._r_trig.storage
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mask = self._r_mask.storage
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dat = self.sink.payload.d
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hit = self.source.payload.hit
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self.comb +=[
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hit.eq((dat & mask) == trig),
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self.source.stb.eq(self.sink.stb),
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self.sink.ack.eq(self.sink.ack),
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self.source.payload.hit.eq(hit)
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]
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class RangeDetector(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.sink = Sink([("d", width)])
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self.source = Source([("hit", 1)])
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self.busy = Signal()
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self._r_low = CSRStorage(width)
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self._r_high = CSRStorage(width)
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###
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low = self._r_low.storage
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high = self._r_high.storage
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dat = self.sink.payload.d
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hit = self.source.payload.hit
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self.comb +=[
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hit.eq((dat >= low) & (dat <= high)),
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self.source.stb.eq(self.sink.stb),
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self.sink.ack.eq(self.sink.ack),
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]
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class EdgeDetector(Module, AutoCSR):
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def __init__(self, width):
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self.width = width
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self.sink = Sink([("d", width)])
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self.source = Source([("hit", 1)])
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self._r_rising_mask = CSRStorage(width)
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self._r_falling_mask = CSRStorage(width)
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self._r_both_mask = CSRStorage(width)
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###
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rising_mask = self._r_rising_mask.storage
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falling_mask = self._r_falling_mask.storage
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both_mask = self._r_both_mask.storage
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dat = self.sink.payload.d
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dat_d = Signal(width)
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rising_hit = Signal()
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falling_hit = Signal()
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both_hit = Signal()
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hit = self.source.payload.hit
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self.sync += dat_d.eq(dat)
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self.comb +=[
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rising_hit.eq(rising_mask & dat & ~dat_d),
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falling_hit.eq(rising_mask & ~dat & dat_d),
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both_hit.eq((both_mask & dat) != (both_mask & dat_d)),
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hit.eq(rising_hit | falling_hit | both_hit),
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self.source.stb.eq(self.sink.stb),
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self.sink.ack.eq(self.sink.ack),
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]
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class Sum(Module, AutoCSR):
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def __init__(self, ports=4):
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self.sinks = [Sink([("hit", 1)]) for p in range(ports)]
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self.source = Source([("hit", 1)])
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self._r_prog_we = CSRStorage()
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self._r_prog_adr = CSRStorage(ports) #FIXME
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self._r_prog_dat = CSRStorage()
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mem = Memory(1, 2**ports)
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lut_port = mem.get_port()
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prog_port = mem.get_port(write_capable=True)
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self.specials += mem, lut_port, prog_port
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###
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# Lut prog
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self.comb +=[
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prog_port.we.eq(self._r_prog_we.storage),
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prog_port.adr.eq(self._r_prog_adr.storage),
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prog_port.dat_w.eq(self._r_prog_dat.storage)
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]
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# Lut read
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for i, sink in enumerate(self.sinks):
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self.comb += lut_port.adr[i].eq(sink.payload.hit)
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# Drive source
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self.comb +=[
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self.source.stb.eq(optree("&", [sink.stb for sink in self.sinks])),
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self.source.payload.hit.eq(lut_port.dat_r),
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[sink.ack.eq(self.source.ack) for sink in self.sinks]
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]
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class Trigger(Module, AutoCSR):
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def __init__(self, width, ports):
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self.width = width
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self.ports = ports
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self.submodules.sum = Sum(len(ports))
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# FIXME : when self.submodules += is used,
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# get_csrs() is not called
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for i, port in enumerate(ports):
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tmp = "self.submodules.port"+str(i)+" = port"
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exec(tmp)
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self.sink = Sink([("d", width)])
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self.source = self.sum.source
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self.busy = Signal()
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###
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for i, port in enumerate(ports):
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self.comb +=[
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port.sink.stb.eq(self.sink.stb),
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port.sink.payload.d.eq(self.sink.payload.d),
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port.source.connect(self.sum.sinks[i])
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] |