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30 lines
897 B
Python
30 lines
897 B
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.clocking import Clocking
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from milkymist.dvisampler.datacapture import DataCapture
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class DVISampler(Module, AutoReg):
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def __init__(self, inversions="", debug_data_capture=True):
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self.submodules.edid = EDID()
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self.sda = self.edid.sda
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self.scl = self.edid.scl
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self.submodules.clocking = Clocking()
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self.clk = self.clocking.clkin
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for datan in "012":
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name = "data" + str(datan)
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cap = DataCapture(8, debug_data_capture)
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setattr(self.submodules, name + "_cap", cap)
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if datan in inversions:
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name += "_n"
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s = Signal(name=name)
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setattr(self, name, s)
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self.comb += [
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cap.pad.eq(s),
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cap.serdesstrobe.eq(self.clocking.serdesstrobe),
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cap.delay_rst.eq(~self.clocking.locked)
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]
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