48 lines
1.3 KiB
Python
48 lines
1.3 KiB
Python
from migen.fhdl.structure import *
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from migen.corelogic.misc import optree
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(S_TO_M, M_TO_S) = range(2)
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# desc is a list of tuples, each made up of:
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# 0) S_TO_M/M_TO_S: data direction
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# 1) string: name
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# 2) int: width
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class Description:
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def __init__(self, *desc):
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self.desc = desc
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def get_names(self, direction, *exclude_list):
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exclude = set(exclude_list)
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return [signal[1]
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for signal in self.desc
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if signal[0] == direction and signal[1] not in exclude]
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class SimpleInterface:
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def __init__(self, desc):
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self.desc = desc
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modules = self.__module__.split(".")
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busname = modules[len(modules)-1]
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for signal in self.desc.desc:
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signame = signal[1]
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setattr(self, signame, Signal(BV(signal[2]), busname + "_" + signame))
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def simple_interconnect_stmts(desc, master, slaves):
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s2m = desc.get_names(S_TO_M)
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m2s = desc.get_names(M_TO_S)
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sl = [getattr(slave, name).eq(getattr(master, name))
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for name in m2s for slave in slaves]
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sl += [getattr(master, name).eq(
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optree("|", [getattr(slave, name) for slave in slaves])
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)
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for name in s2m]
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return sl
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class SimpleInterconnect:
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def __init__(self, master, slaves):
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self.master = master
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self.slaves = slaves
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def get_fragment(self):
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return Fragment(simple_interconnect_stmts(self.master.desc, self.master, self.slaves))
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