Sebastien Bourdeauducq 4164fb4ac9 bus/csr: configurable data width		2012-08-26 21:19:34 +02:00
..
__init__.py	CSR bus definitions	2011-12-05 00:16:44 +01:00
asmibus.py	bus/asmibus: fix per-port tag generation	2012-07-12 19:37:50 +02:00
csr.py	bus/csr: configurable data width	2012-08-26 21:19:34 +02:00
dfi.py	bus/dfi: reset active low signals to 1	2012-04-01 17:43:24 +02:00
simple.py	bus: add interconnect statements function	2012-02-17 23:51:32 +01:00
transactions.py	bus: generic transaction model	2012-03-08 18:14:06 +01:00
wishbone.py	x.bv.width -> len(x)	2012-07-13 18:32:54 +02:00
wishbone2asmi.py	bus/wishbone2asmi: fix cache tag size	2012-05-15 15:18:03 +02:00
wishbone2csr.py	bus/csr: configurable data width	2012-08-26 21:19:34 +02:00