Florent Kermarrec 3b47d4a479 tools/litex_jtag_uart: add openocd config and telnet port parameters.		2020-05-27 08:59:12 +02:00
..
boards	platforms/targets: keep in sync with litex-boards.	2020-05-21 09:14:33 +02:00
build	tools: add litex_jtag_uart to create a virtual uart for the jtag uart.	2020-05-25 10:21:06 +02:00
gen	gen/fhdl/verilog: explicitly define input/output/inout wires.	2020-05-05 16:58:33 +02:00
soc	cpus: remove common cpu variants/extensions definition and simplify variant check.	2020-05-26 09:36:44 +02:00
tools	tools/litex_jtag_uart: add openocd config and telnet port parameters.	2020-05-27 08:59:12 +02:00
__init__.py	litex/__init__.py: remove retro-compat > 6 months old.	2020-04-30 21:31:58 +02:00