Florent Kermarrec 571ce5791a litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization ... self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.		2015-06-10 12:14:48 +02:00
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__init__.py	…
crg.py	…
trx.py	litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization	2015-06-10 12:14:48 +02:00