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Build your hardware, easily!
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Florent Kermarrec 3f43a49382 soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b 
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
 		2015-11-10 16:51:51 +01:00
litex soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b 2015-11-10 16:51:51 +01:00
.gitignore litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00
.gitmodules soc/software: remove libunwind 2015-11-10 12:16:34 +01:00
MANIFEST.in litex: get verilator simulation working and add sim target as example 2015-11-07 23:51:37 +01:00
README README: update 2015-11-10 11:33:11 +01:00
setup.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00

README 

                       __   _ __      _  __
                      / /  (_) /____ | |/_/
                     / /__/ / __/ -_)>  <
                    /____/_/\__/\__/_/|_|

                Build your hardware, easily!
                Copyright 2015 Enjoy-Digital

[> Intro
---------
LiteX is an alternative (fork) to Migen/MiSoC maintained and used by Enjoy-Digital
to build our cores, integrate them in complete SoC and load/flash them to the
hardware.

The structure of LiteX is kept close to Migen/MiSoC to ease collaboration
between projects.

[> License
-----------
LiteX is copyright (c) 2015 Enjoy-Digital under BSD Lisense.
Since it is based on MiSoC/Migen, please also refer to LICENSE files in soc/gen 
directories or git history to get correct copyrights.

[> Sub-packages
-----------
gen:
  Provides tools and simple modules to generate HDL.

build:
  Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
  simulate HDL code or full SoCs.

soc:
  Provides definitions/modules to build cores (bus, bank, flow), cores and tools
  to build a SoC from such cores.

boards:
  Provides platforms and targets for the supported boards.

[> Quick start guide
--------------------
0. If cloned from Git without the --recursive option, get the submodules:
  git submodule update --init

1. Install Python 3.3+ and FPGA vendor's development tools and JTAG tools.

2. Compile and install binutils. Take the latest version from GNU.
  mkdir build && cd build
  ../configure --target=lm32-elf
  make
  make install

3. (Optional, only if you want to use a lm32 CPU in you SoC)
  Compile and install GCC. Take gcc-core and gcc-g++ from GNU
  (version 4.5 or >=4.9).
  rm -rf libstdc++-v3
  mkdir build && cd build
  ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
    --disable-libssp
  make
  make install

4. Build the target of your board...:
  Go to boards/targets and execute the target you want to build

5. ... and/or install Verilator and test LiteX on your computer:
  Download and install Verilator: http://www.veripool.org/
  Go to boards/targets
  ./sim.py

6. Run a terminal program on the board's serial port at 115200 8-N-1.
  You should get the BIOS prompt.

[> Contact
E-mail: florent [AT] enjoy-digital.fr