litex/misoclib/com
Florent Kermarrec 4329e3e1b9 liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705) 2015-04-12 14:28:17 +02:00
..
gpio move gpio from cpu.peripherals to com 2015-04-02 17:17:33 +08:00
liteeth liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705) 2015-04-12 14:28:17 +02:00
liteusb liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6) 2015-03-22 11:11:37 +01:00
spi com/spi: use .format in tb 2015-03-03 10:44:05 +01:00
uart uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty). 2015-03-12 16:57:38 +01:00
__init__.py misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00