318 lines
17 KiB
Python
318 lines
17 KiB
Python
#
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# This file is part of LiteX
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#
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# Copyright (c) 2019-2024 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2024 MoTeC <www.motec.com.au>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.soc.cores.hyperbus import HyperRAM
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def c2bool(c):
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return {"-": 1, "_": 0}[c]
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class Pads: pass
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class HyperRamPads:
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def __init__(self, dw=8):
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self.clk = Signal()
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self.rst_n = Signal()
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self.cs_n = Signal()
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self.dq = Record([("oe", 1), ("o", dw), ("i", dw)])
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self.rwds = Record([("oe", 1), ("o", dw//8), ("i", dw//8)])
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class TestHyperRAM(unittest.TestCase):
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def test_hyperram_syntax(self):
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pads = Record([("clk", 1), ("rst_n", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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hyperram = HyperRAM(pads)
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pads = Record([("clk_p", 1), ("clk_n", 1), ("rst_n", 1), ("cs_n", 1), ("dq", 8), ("rwds", 1)])
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hyperram = HyperRAM(pads)
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def test_hyperram_write_latency_5_2x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "----__________________________________________________________------"
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dq_oe = "______------------____________________________________--------______"
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dq_o = "0000002000048d0000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "______________________________________________________--------______"
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rwds_o = "________________________________________________________----________"
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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if (yield dut.pads.dq.oe):
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(dw=8), latency=5, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_write_latency_5_2x_sys2x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "________________--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "_------------__________________________________________________________------"
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dq_oe = "_______________------------____________________________________--------______"
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dq_o = "0000000000000002000048d0000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "_______________________________________________________________--------______"
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rwds_o = "_________________________________________________________________----________"
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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#if (yield dut.pads.dq.oe):
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# self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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for i in range(128):
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yield
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dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed", clk_ratio="2:1")
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generators = {
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"sys" : fpga_gen(dut),
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"sys2x" : hyperram_gen(dut),
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}
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clocks = {
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"sys" : 4,
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"sys2x" : 2,
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}
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run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
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def test_hyperram_write_latency_6_2x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "----__________________________________________________________________------"
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dq_oe = "______------------____________________________________________--------______"
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dq_o = "0000002000048d000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "______________________________________________________________--------______"
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rwds_o = "________________________________________________________________----________"
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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if (yield dut.pads.dq.oe):
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), latency=6, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_write_latency_7_2x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "----__________________________________________________________________________------"
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dq_oe = "______------------____________________________________________________--------______"
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dq_o = "0000002000048d00000000000000000000000000000000000000000000000000000000deadbeef000000"
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rwds_oe = "______________________________________________________________________--------______"
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rwds_o = "________________________________________________________________________----________"
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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if (yield dut.pads.dq.oe):
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_write_latency_7_1x(self):
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def fpga_gen(dut):
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yield from dut.bus.write(0x1234, 0xdeadbeef, sel=0b1001)
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yield
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--_______"
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cs_n = "----______________________________________________------"
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dq_oe = "______------------________________________--------______"
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dq_o = "0000002000048d0000000000000000000000000000deadbeef000000"
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rwds_oe = "__________________________________________--------______"
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rwds_o = "____________________________________________----________"
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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if (yield dut.pads.dq.oe):
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="variable")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_read_latency_5_2x(self):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________________"
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dq_o = "000000a000048d000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "000000000000000000000000000000000000000000000000000000deadbeefcafefade0000000000000000"
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rwds_oe = "______________________________________________________________________________________"
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rwds_i = "______________________________________________________--__--__--__--__________________"
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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yield dut.pads.rwds.i.eq(c2bool(rwds_i[i]))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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if (yield dut.pads.dq.oe):
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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yield
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dut = HyperRAM(HyperRamPads(), latency=5, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_read_latency_6_2x(self):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________________________"
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dq_o = "000000a000048d00000000000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "00000000000000000000000000000000000000000000000000000000000000deadbeefcafefade0000000000000000"
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rwds_oe = "______________________________________________________________________________________________"
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rwds_i = "______________________________________________________________--__--__--__--__________________"
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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yield dut.pads.rwds.i.eq(c2bool(rwds_i[i]))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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if (yield dut.pads.dq.oe):
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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yield
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dut = HyperRAM(HyperRamPads(), latency=6, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_read_latency_7_2x(self):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__--_____"
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cs_n = "----______________________________________________________________________________________________----"
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dq_oe = "______------------____________________________________________________________________________________"
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dq_o = "000000a000048d0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
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dq_i = "0000000000000000000000000000000000000000000000000000000000000000000000deadbeefcafefade0000000000000000"
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rwds_oe = "______________________________________________________________________________________________________"
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rwds_i = "______________________________________________________________________--__--__--__--__________________"
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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yield dut.pads.rwds.i.eq(c2bool(rwds_i[i]))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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if (yield dut.pads.dq.oe):
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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yield
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dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="fixed")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_read_latency_7_1x(self):
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def fpga_gen(dut):
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dat = yield from dut.bus.read(0x1234)
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self.assertEqual(dat, 0xdeadbeef)
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def hyperram_gen(dut):
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clk = "_______--__--__--__--__--__--__--__--__--__--__--__--__--__--__--__-______"
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cs_n = "----________________________________________________________________------"
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dq_oe = "______------------________________________________________________________"
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dq_o = "000000a000048d000000000000000000000000000000000000000000000000000000000000"
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dq_i = "0000000000000000000000000000000000000000deadbeefcafefade000000000000000000"
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rwds_oe = "__________________________________________________________________________"
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rwds_i = "________________________________________--__--__--__--____________________"
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yield
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for i in range(len(clk)):
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yield dut.pads.dq.i.eq(int(dq_i[2*(i//2):2*(i//2)+2], 16))
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yield dut.pads.rwds.i.eq(c2bool(rwds_i[i]))
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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if (yield dut.pads.dq.oe):
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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yield
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dut = HyperRAM(HyperRamPads(), latency=7, latency_mode="variable")
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")
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def test_hyperram_reg_write(self):
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def fpga_gen(dut):
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yield dut.core.reg.adr.eq(2)
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yield dut.core.reg.dat_w.eq(0x1234)
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yield
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yield dut.core.reg.stb.eq(1)
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yield dut.core.reg.we.eq(1)
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while (yield dut.core.reg.ack) == 0:
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yield
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yield dut.core.reg.stb.eq(0)
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def hyperram_gen(dut):
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clk = "___________--__--__--__--___________"
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cs_n = "--------__________________----------"
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dq_oe = "__________----------------__________"
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dq_o = "000000000060000100000012340000000000"
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rwds_oe = "____________________________________"
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rwds_o = "____________________________________"
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yield
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for i in range(len(clk)):
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self.assertEqual(c2bool(clk[i]), (yield dut.pads.clk))
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self.assertEqual(c2bool(cs_n[i]), (yield dut.pads.cs_n))
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self.assertEqual(c2bool(dq_oe[i]), (yield dut.pads.dq.oe))
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if (yield dut.pads.dq.oe):
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self.assertEqual(int(dq_o[2*(i//2):2*(i//2)+2], 16), (yield dut.pads.dq.o))
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self.assertEqual(c2bool(rwds_oe[i]), (yield dut.pads.rwds.oe))
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self.assertEqual(c2bool(rwds_o[i]), (yield dut.pads.rwds.o))
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yield
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dut = HyperRAM(HyperRamPads(), with_csr=False)
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run_simulation(dut, [fpga_gen(dut), hyperram_gen(dut)], vcd_name="sim.vcd")# |