Commit Graph

14 Commits

Author SHA1 Message Date
Florent Kermarrec c554752e8a soc/cores/hyperbus: Add automatic read burst detection. 2024-08-30 11:53:14 +02:00
Florent Kermarrec fac80c3a51 soc/cores/hyperbus: Full rewrite of HyperRAM core.
Rewriting the HyperRAM core to improve its design and functionality. The
old core grew complex over time without a clear structure. This new version
offers:
- IO registers on all signals for better performance.
- Flexible clocking options.
- Simplified architecture.
- Easier to extend with new features.

This rewrite provides a base for future development.
2024-08-29 12:54:09 +02:00
Florent Kermarrec a88cee70c8 test/test_hyperbus: Update. 2024-08-21 19:22:56 +02:00
Florent Kermarrec 5587f5954d test/test_hyperbus: Add 2:1 test. 2024-08-21 15:00:11 +02:00
Florent Kermarrec 50f0a1057c soc/cores/hyperbus: Do some tests with sys_2x, seems working. 2024-08-21 10:57:36 +02:00
Florent Kermarrec 60f83b71fa soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided). 2024-08-20 21:54:15 +02:00
Florent Kermarrec 76cf004913 test/test_hyperbus: Update. 2024-08-20 15:17:36 +02:00
Florent Kermarrec 3978af9c39 test/test_hyperbus: Update. 2024-04-16 11:12:30 +02:00
Florent Kermarrec 6216bd4e99 cores/hyperbus: Add latency_mode parameter and test different latencies/modes in simulation. 2024-04-15 10:32:13 +02:00
Florent Kermarrec b192103822 cores/hyperbus: Fix bytes order on register writes. 2024-04-12 16:06:26 +02:00
Florent Kermarrec fb519ac260 test/test_hyperbus: Add test_hyperram_reg_write. 2024-04-12 15:21:57 +02:00
Florent Kermarrec dbde036162 soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.
The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX
which avoid an additional dependency.
2022-03-01 09:11:55 +01:00
Florent Kermarrec 6f8f0d2346 litex_setup: add litehyperbus and remove hyperbus core/test. 2020-05-19 15:49:25 +02:00
Florent Kermarrec 4990bf33c0 soc/core: simplify/cleanup HyperRAM core
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).

Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
2019-08-16 14:04:58 +02:00