Sean Cross 45a649be9b tools: vexriscv_debug: add debug bridge ... Add a bridge that uses litex_server to go from openocd to wishbone. Signed-off-by: Sean Cross <sean@xobs.io>		2018-07-06 16:08:06 +08:00
..
cores	cores/cpu/vexriscv: create variants: None and "debug", some cleanup	2018-07-05 17:31:23 +02:00
integration	cores/cpu/vexriscv: create variants: None and "debug", some cleanup	2018-07-05 17:31:23 +02:00
interconnect	replace litex.gen imports with migen imports	2018-02-23 13:38:19 +01:00
software	bios/sdram: also check for last read of scan to choose optimal window	2018-07-02 14:12:27 +02:00
tools	tools: vexriscv_debug: add debug bridge	2018-07-06 16:08:06 +08:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
MISOC_LICENSE	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00