litex/verilog
Michael Walle 47baad4fe1 lm32: replace clogb2 by builtin $clog2
This function is fixed in ISE since version 14.1 (see AR #44586). If the
builtin function is used, the design can be simulated with Icarus Verilog.

Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:07:28 +01:00
..
generic framebuffer: fix FIFO read clocking 2012-07-07 11:30:27 +02:00
lm32 lm32: replace clogb2 by builtin $clog2 2012-11-14 14:07:28 +01:00
m1crg Define clock domains instead of passing extra clocks as regular signals 2012-09-11 00:21:07 +02:00
minimac3 Remove some boilerplate 2012-05-24 19:22:27 +02:00
s6ddrphy asmicon: skeleton 2012-03-14 18:26:05 +01:00