Florent Kermarrec 497413664e libbase/progress: reduce to 40 HASHES_PER_LINE.		2020-06-25 09:56:13 +02:00
..
boards	platforms/genesys2: add usb_fifo.	2020-06-23 18:01:51 +02:00
build	build/sim/core/modules: fix compilation warnings	2020-06-16 01:06:11 +02:00
gen	gen/fhdl/verilog: explicitly define input/output/inout wires.	2020-05-05 16:58:33 +02:00
soc	libbase/progress: reduce to 40 HASHES_PER_LINE.	2020-06-25 09:56:13 +02:00
tools	litex_term: keep and reduce inter-frame delay to 1e-5.	2020-06-23 17:20:12 +02:00
__init__.py	litex/__init__.py: remove retro-compat > 6 months old.	2020-04-30 21:31:58 +02:00