Florent Kermarrec 4a4e82b5f6 etherbone: wishbone writes seems OK in simulation		2015-02-11 20:54:32 +01:00
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core	etherbone: wishbone writes seems OK in simulation	2015-02-11 20:54:32 +01:00
generic	etherbone: add record depacketizer/packetizer (wip)	2015-02-11 16:21:06 +01:00
mac	create Port class and remove connect method of mac/ip/udp Ports	2015-02-10 15:37:29 +01:00
phy	phy: add hw_init_reset (useful when used without CPU)	2015-02-10 16:03:07 +01:00
test	etherbone: wishbone writes seems OK in simulation	2015-02-11 20:54:32 +01:00
__init__.py	reorganize core files	2015-02-04 19:57:20 +01:00
common.py	etherbone: code wishbone master	2015-02-11 19:44:02 +01:00