71 lines
1.8 KiB
Python
71 lines
1.8 KiB
Python
from liteeth.common import *
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from migen.bus import wishbone
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class LiteEthEtherboneWishboneMaster(Module):
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def __init__(self):
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self.wr_sink = wr_sink = Sink(eth_etherbone_mmap_description(32))
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self.rd_sink = rd_sink = Sink(eth_etherbone_mmap_description(32))
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self.wr_source = wr_source = Source(eth_etherbone_mmap_description(32))
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self.rd_source = rd_source = Source(eth_etherbone_mmap_description(32))
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self.bus = bus = wishbone.Interface()
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###s
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data = FlipFlop(32)
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self.submodules += data
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self.comb += data.d.eq(bus.dat_r)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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wr_sink.ack.eq(1),
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rd_sink.ack.eq(1),
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If(wr_sink.stb & wr_sink.sop,
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wr_sink.ack.eq(0),
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NextState("WRITE_DATA")
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).Elif(rd_sink.stb & rd_sink.sop,
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rd_sink.ack.eq(0),
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NextState("READ_DATA")
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)
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)
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fsm.act("WRITE_DATA",
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bus.adr.eq(wr_sink.addr),
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bus.dat_w.eq(wr_sink.data),
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bus.sel.eq(wr_sink.be),
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bus.stb.eq(wr_sink.stb),
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bus.we.eq(1),
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bus.cyc.eq(1),
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If(bus.stb & bus.ack,
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wr_sink.ack.eq(1),
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If(wr_sink.eop,
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NextState("IDLE")
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)
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)
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)
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fsm.act("READ_DATA",
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bus.adr.eq(rd_sink.addr),
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bus.sel.eq(rd_sink.be),
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bus.stb.eq(rd_sink.stb),
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bus.cyc.eq(1),
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If(bus.stb & bus.ack,
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data.ce.eq(1),
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NextState("SEND_DATA")
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)
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)
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fsm.act("SEND_DATA",
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wr_source.stb.eq(rd_sink.stb),
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wr_source.sop.eq(rd_sink.sop),
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wr_source.eop.eq(rd_sink.eop),
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wr_source.base_addr.eq(rd_sink.base_addr),
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wr_source.addr.eq(rd_sink.addr),
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wr_source.count.eq(rd_sink.count),
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wr_source.be.eq(rd_sink.be),
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wr_source.data.eq(data.q),
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If(wr_source.stb & wr_source.ack,
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rd_sink.ack.eq(1),
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If(wr_source.eop,
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NextState("IDLE")
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).Else(
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NextState("READ_DATA")
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)
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)
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)
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