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litex/migen
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Sebastien Bourdeauducq 4ada2ead05 fhdl/specials/Memory: automatic name# 2013-03-12 15:58:39 +01:00
..
actorlib bank: automatic register naming 2013-03-12 15:45:24 +01:00
bank bank: automatic register naming 2013-03-12 15:45:24 +01:00
bus bank: automatic register naming 2013-03-12 15:45:24 +01:00
fhdl fhdl/specials/Memory: automatic name# 2013-03-12 15:58:39 +01:00
flow bank: automatic register naming 2013-03-12 15:45:24 +01:00
genlib genlib: clock domain crossing elements 2013-02-23 19:03:35 +01:00
pytholite Use common definition for FinalizeError 2013-03-09 19:03:13 +01:00
sim New 'specials' API 2013-02-22 17:56:35 +01:00
uio uio/ioo: fix specials 2013-02-25 23:13:38 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00