litex/migen/fhdl
Sebastien Bourdeauducq 4ada2ead05 fhdl/specials/Memory: automatic name# 2013-03-12 15:58:39 +01:00
..
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
module.py fhdl/module: replace autofragment 2013-03-10 19:27:55 +01:00
namer.py New 'specials' API 2013-02-22 17:56:35 +01:00
specials.py fhdl/specials/Memory: automatic name# 2013-03-12 15:58:39 +01:00
structure.py fhdl/module: replace autofragment 2013-03-10 19:27:55 +01:00
tools.py fhdl/tools/flat_iteration: generalize 2013-03-09 23:03:15 +01:00
tracer.py bank: automatic register naming 2013-03-12 15:45:24 +01:00
verilog.py fhdl/verilog: tristate outputs are always wire 2013-03-06 11:30:52 +01:00
visit.py fhdl: support nested statement lists 2013-01-05 14:18:15 +01:00