Florent Kermarrec 4b77b850ce add SpiFlashSingle and rename SpiFlash to SpiFlashDualQuad		2017-01-26 13:28:18 +01:00
..
cpu	initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)	2016-04-01 00:09:17 +02:00
flash	add SpiFlashSingle and rename SpiFlash to SpiFlashDualQuad	2017-01-26 13:28:18 +01:00
spi	soc/cores: fix spi	2016-04-19 06:49:23 +02:00
uart	build/sim: adapt verilator simulation to new stream signals	2016-04-07 08:56:53 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
gpio.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
identifier.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00
timer.py	for now use our fork of migen (to be able to simulate our designs)	2015-11-13 18:31:46 +01:00