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4b8d9b67f3
litex
/
misoclib
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mem
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litesata
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phy
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Florent Kermarrec
04c64eb1d8
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
2015-06-26 00:20:58 +02:00
..
k7
litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
2015-06-10 12:14:48 +02:00
__init__.py
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
2015-06-26 00:20:58 +02:00
ctrl.py
litesata: do some cleanup and prepare for RAID
2015-05-23 14:08:56 +02:00
datapath.py