litex/litex/soc
2020-12-21 18:44:10 +01:00
..
cores cores/cpu/vexriscv_smp add AES support 2020-12-18 12:10:33 +01:00
doc soc: change default CSR bus data-width to 32. 2020-10-07 16:38:49 +02:00
integration integration/export/get_csr_header: don't generate replace/write fields access functions when CSR is read only. 2020-12-14 10:51:37 +01:00
interconnect soc/interconnect/axi: fix AXIInterface.get_ios(). 2020-12-21 08:51:04 +01:00
software software/demo: add short README. 2020-12-21 18:44:10 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00