Florent Kermarrec 4fed1cc7a7 soc/integration/builder: move csr_csv generation outside of generate include ... we mostly use csr_csv for designs without CPU		2015-12-03 15:16:22 +01:00
..
boards	boards/nexys_video: use ethernet constraints similar to kc705	2015-12-01 11:50:05 +01:00
build	build/sim/verilator: add toolchain_path parameter	2015-12-02 15:35:55 +01:00
gen	gen/fhdl/verilog: add regular comb parameter to allow implementation of simulation code (for icarus)	2015-12-02 14:16:23 +01:00
soc	soc/integration/builder: move csr_csv generation outside of generate include	2015-12-03 15:16:22 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00