litex/litex/soc
Sean Cross 5079a3c32e uart: add BridgedUart
This version of the UART adds a second, compatible UART after
the first.  This maintians software compatibility, and allows a
program running on the other side of the litex bridge to act as
a terminal emulator by manually reading and writing the second
UART.

Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-12 19:52:42 +10:00
..
cores uart: add BridgedUart 2020-01-12 19:52:42 +10:00
integration soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description 2020-01-02 09:41:47 +01:00
interconnect wishbone/Cache: avoid REFILL_WRTAG state to improve speed. 2020-01-10 14:25:07 +01:00
software bios/sdram: add memspeed 2020-01-10 14:25:46 +01:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00