This website requires JavaScript.
Explore
Help
Sign In
Hardware
/
litex
mirror of
https://github.com/enjoy-digital/litex.git
Watch
1
Star
0
Fork
You've already forked litex
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
50e857e99c
litex
/
misoclib
/
soc
History
whitequark
4b6bd43d8e
Enable ror, ffl1 and addc for OR1K.
2015-07-30 10:55:01 +03:00
..
__init__.py
Don't build base libraries and BIOS with -fPIC after all.
2015-07-29 12:09:05 +03:00
cpuif.py
Enable ror, ffl1 and addc for OR1K.
2015-07-30 10:55:01 +03:00
sdram.py
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
2015-06-19 08:39:37 +02:00