Florent Kermarrec 50e857e99c sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies. ... Built on top of S6HalfRateDDRPHY, exposes a 4 phases DFI interface to the controller with a 2x slower clock. Validated on the Numato Lab opsis board (50MHz sys_clk/ DDR400), should also work on the Novena laptop (same DDR3 module).		2015-08-22 12:17:48 +02:00
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com	liteeth/phy: fix autodetect (clk_freq not necessary passed in kwargs)	2015-08-22 12:08:49 +02:00
cpu	mor1kx: enable ADDC, CMOV and FFL1 instructions	2015-07-29 00:08:21 +08:00
mem	sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies.	2015-08-22 12:17:48 +02:00
soc	Enable ror, ffl1 and addc for OR1K.	2015-07-30 10:55:01 +03:00
tools	litecores: add -Ob option to make.py (allow to build with yosys for example)	2015-08-19 01:17:37 +02:00
video	misoclib/video/dvisampler: add fifo_depth parameter	2015-07-13 11:03:33 +02:00
__init__.py	rename milkymist-ng to MiSoC	2013-11-09 15:27:32 +01:00
mxcrg.v	misoclib: integrate mxcrg.py in mlabs_video target, remove others directory	2015-07-24 23:16:45 +02:00