Florent Kermarrec 50e857e99c sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies. ... Built on top of S6HalfRateDDRPHY, exposes a 4 phases DFI interface to the controller with a 2x slower clock. Validated on the Numato Lab opsis board (50MHz sys_clk/ DDR400), should also work on the Novena laptop (same DDR3 module).		2015-08-22 12:17:48 +02:00
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flash	spiflash: fix miso bitbang with large DQ	2015-05-06 00:05:25 +08:00
litesata	litecores: add -Ob option to make.py (allow to build with yosys for example)	2015-08-19 01:17:37 +02:00
sdram	sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies.	2015-08-22 12:17:48 +02:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00