Florent Kermarrec 50e857e99c sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies. ... Built on top of S6HalfRateDDRPHY, exposes a 4 phases DFI interface to the controller with a 2x slower clock. Validated on the Numato Lab opsis board (50MHz sys_clk/ DDR400), should also work on the Novena laptop (same DDR3 module).		2015-08-22 12:17:48 +02:00
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core	sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon	2015-06-17 15:30:30 +02:00
frontend	wishbone2lasmi: fix "READ_DATA" state	2015-07-09 10:40:32 +02:00
phy	sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies.	2015-08-22 12:17:48 +02:00
test	global: more pep8	2015-04-13 18:02:26 +02:00
__init__.py	global: pep8 (replace tabs with spaces)	2015-04-13 16:19:55 +02:00
module.py	sdram/module: cleanup indent	2015-08-20 22:15:06 +02:00