30 lines
808 B
Python
30 lines
808 B
Python
from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.frontend.common import *
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from migen.genlib.roundrobin import *
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class LiteSATAArbiter(Module):
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def __init__(self, users, master):
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self.rr = RoundRobin(len(users))
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self.submodules += self.rr
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self.grant = self.rr.grant
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cases = {}
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for i, slave in enumerate(users):
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sink, source = slave.sink, slave.source
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start = Signal()
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done = Signal()
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ongoing = Signal()
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self.comb += [
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start.eq(sink.stb & sink.sop),
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done.eq(source.stb & source.last & source.eop & source.ack)
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]
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self.sync += \
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If(start,
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ongoing.eq(1)
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).Elif(done,
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ongoing.eq(0)
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)
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self.comb += self.rr.request[i].eq((start | ongoing) & ~done)
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cases[i] = [users[i].connect(master)]
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self.comb += Case(self.grant, cases)
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